Continuously reducing the size of solid-state memory architecture is an effective way to increase the capacity of such memories for a given amount of circuit real estate. However, the resulting feature size can give rise to design and process challenges. For example, voltages impressed on conductors located close together can provide a strong electric field that contributes to the breakdown of thin dielectric layers. This may become especially significant during erase and program operations.
For example, considering programming operations for some memory structures, the difference in potential between wordline conductors and global source-select-gate (global SGS) or global drain-select-gate (global SGD) conductors may be less than 20V, and the SGS bias can be trimmed to further reduce this amount.
As a matter of contrast, during an erase operation, the difference between wordlines and global SGS/SGD conductors may reach ˜24V. This is because the pass gate for string drivers may be biased to +4V (Vpass) and higher in order to fully discharge the wordlines. To prevent the discharge of select gates, the global SGS/SGD conductors are biased to the same voltage as Vpass. After a nominal settling time, the array substrate voltage (Iso-Pwell) rises to about 20V for erase, which couples the local SGS and SGD conductors to about −24V. Thus, the wordlines are at about zero volts, while the local SGD/SGS conductors are at 24V.
Therefore, the dielectric stress in semiconductor memory may be more severe during erase operations than for programming operations, and the possibility of dielectric breakdown between two polysilicon conductors increases, since the electrical field is about 4.8 MV/cm (for 50 nm technology) and 6.86 MV/cm (for 35 nm technology), assuming the conductor spacing is about the same as the feature size. These field values are both close to the silicon dioxide breakdown voltage quoted in various references. The possibility of breakdown further increases with the stress time, which may be several milliseconds for erase operations. Thus, there is a need for apparatus, systems, and methods that provide a mechanism to reduce the dielectric stress encountered during memory erase operations. Readers interesting in learning more about the interaction between wordlines and gate-select lines are encouraged to consult U.S. Pat. Nos. 7,035,143 and 7,068,543, incorporated herein by reference in their entirety.